The invention relates to a semiconductor memory of the dynamic random access type (DRAM), having memory cells disposed in at least four matrix memory cell arrays in a memory field. The memory cells are combined in addressable units of bit lines and word lines. Each memory cell array is allocated a row decoder for selection of one of the word lines in the memory cell array, and a column decoder for selection of one of the bit lines in the memory cell array. The row decoders in the at least four memory cell arrays for selection of one of the word lines are connected to a row selection signal line for transmission of a row selection signal. The invention also relates to a method for actuating a memory cell in such a semiconductor memory.
Modern semiconductor memories of the dynamic random access type (DRAM) require more area on semiconductor chips, despite the fact that structures for the rapidly increasing memory capacities are becoming smaller, and the memory cell fields are thus becoming larger. However, the area requirement is associated with considerable production costs. Apart from the memory cell fields, a not insignificant proportion of the area of a semiconductor memory chip is occupied by control, address and data lines, some of which are disposed alongside those fields and are becoming broader with the memory capacity of the semiconductor memory, and by control devices which are required for operation of the data memory.
A literature reference entitled: xe2x80x9cA 4 kxc3x978 Dynamic RAM with Self-Refreshxe2x80x9d, by E. Reese, et. al., in IEEE Journal of Solid-State Circuits, volume SC-16, No. 5, October 1981, pages 479 to 487, describes a 64 k semiconductor memory in which the memory cell field includes four memory cell arrays. Row and column decoders are disposed on different sides of the memory cell arrays. Both the column addresses and data are transmitted in multiplexed form on the internal bus. A separate bus is available to provide the column addresses.
U.S. Pat. No. 4,195,357 discloses a semiconductor memory in which the first 8 bits of an address in a memory cell and the next 8 bits of the address of the memory cell are applied after external multiplexing. A row address latch is available within the integrated semiconductor memory for the first 8 bits, and a column address latch is available for the next 8 bits.
It is accordingly an object of the invention to provide a semiconductor memory of the dynamic random access type (DRAM) and a method for actuating a memory cell, which overcome the hereinafore-mentioned disadvantages of the heretofore-known devices and methods of this general type and in which more area is available for memory cells.
With the foregoing and other objects in view there is provided, in accordance with the invention, a semiconductor memory of the dynamic random access type, comprising memory cells combined in addressable units of bit lines and word lines. The memory cells are disposed in at least four matrix memory cell arrays in a memory field. The memory cell arrays have outer edge areas and the memory field has an edge area. Each of the memory cell arrays has two sides and each of the sides is disposed opposite one side of another of the memory cell arrays. Row decoders are each assigned to a respective one of the memory cell arrays for selection of one of the word lines in the memory cell array, and column decoders are each assigned to a respective one of the memory cell arrays for selection of one of the bit lines in the memory cell array. The column decoders are each disposed at the outer edge area of the assigned memory cell array and at the edge area of the memory field. A row selection signal line is provided for transmission of a row selection signal. The row selection signal line is connected to the row decoders in the at least four memory cell arrays for selection of one of the word lines. The row selection signal line and the row decoders are disposed between respective opposite sides of the memory cell arrays. The column decoders for selection of one of the bit lines in the assigned memory cell arrays are connected to the row selection signal line for transmission of a column selection signal.
The invention proposes the possibility of saving a complete data bus, namely the column selection signal line (COLUMN), which is generally disposed at right angles to the row selection signal line (ROW), by using the row selection signal line for two purposes. This releases considerable surface areas of the chip, as a result of which the memory cell fields can be further enlarged or the structures made smaller, thus leading to cost savings.
In accordance with a concomitant mode of the invention, the row decoder is constructed in such a way that the row selection signal which is transmitted to it through the row selection signal line can be stored. This makes it possible for the row selection signal (ROW address) to be transmitted first of all on the row selection signal line, after which the column selection signal (COLUMN address) can be transmitted on the same row selection signal line. The memory cells can thus be actuated together with the temporarily stored row selection signal.
With the objects of the invention in view, there is also provided a method for actuating a memory cell disposed in such a semiconductor memory of the dynamic random access type (DRAM), which comprises transmitting a row selection signal to a row decoder assigned to a memory cell array for selection of a word line, and transmitting a column selection signal to a column decoder assigned to the memory cell array for selection of a bit line, at mutually different times through a selection signal line.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a semiconductor memory of the dynamic random access type (DRAM) and a method for actuating a memory cell, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.